$6.4M to IBM to Research Non-Thermionic Transistors
In conventional silicon transistors, a certain finite voltage swing on the order of 150-200 mV (for high performance devices) is needed to switch a device between the on and off states. Reducing that number would enable drastic improvements in power consumption, because modern chips have many millions of transistors – but the fundamental physics of thermionic emission over an energy barrier is in the way.
International Business Machines (IBM) Corporation of NY recently received a contract option for $6.4 million under a DARPA program known as “Steep-subthreshold-slope Transistors for Electronics with Extremely-low Power (STEEP). The goal is to develop novel transistor technologies based on non-thermionic switching, allowing manufacturers to build high-performance logic circuits with very low power consumption. At this time $4.5 million has been obligated by Det 1 AFRL/PKDA at Wright-Patterson Air Force Base, OH (FA8650-08-C-7806).
IBM’s new devices under this DARPA-funded research program will utilize a fundamentally different mechanism of operation based upon quantum mechanical tunneling, which allows them be switched on and off over a much smaller voltage range. Such devices have previously been demonstrated, but only at extremely low performance levels. The goal of this program is to build a device that meets the performance criteria for much higher-performance computing.
Which is nice – but why does this really matter in the field? Consider 3 factors making themselves felt on the front lines, plus one above them, and another behind:
A number of engineering challenges will remain even if the DARPA experiment is somewhat successful, and the development of useful equipment from this effort will take years if it succeeds at all. Nevertheless, the implications could be significant on a number of fronts. DARPA spokesman said:
“High power efficiencies are an important requirement for a wide variety of critical military systems including communications, sensors and space applications. If DARPA is successful in developing ultra-low-power, high-performance electronic circuits based on the novel ultra-low voltage transistor concepts being explored, the likely number of applications will be extremely wide – using vastly less power while still providing excellent performance will be useful both for the military’s highly challenging applications mentioned above and also for many consumer applications.”
Consider, for instance, the increasing array of digitized devices soldiers are carrying around: night vision, GPS, PDAs with force tracking software, wrist displays that stream UAV video, some rifle scopes, et. al. These devices are useful, but they all require batteries and backup batteries – and the result is far too many pounds of weight added to each soldier’s carrying load. The only ways out is to improve the batteries by orders of magnitude, improve item power consumption by orders of magnitude, or both. Or, to remove many of the devices themselves. Very low-voltage transistors could make a big difference here. The question is whether IBM’s new chip architecture would be able to take the kind of punishment dished out by life in the field, even if the chip experiments are successful and engineering advances grew the number of transistors to required levels.
Another front-line trend is the increasing use of armored vehicles in surveillance mode, in order to leverage their advanced sensors. Adding advanced surveillance electronics means adding power requirements, however, which in turn requires running the engine so that its generator can keep everything running without killing the vehicle’s battery. At which point, the need for vulnerable fuel convoys goes up, and you can kiss your hopes of unobtrusive observation goodbye as the big diesel engine roars away. Auxiliary Power Units can solve some of this problem, and are being installed on vehicles like M1 Abrams tanks, but if the power load keeps increasing they, too, will hit their limits. Silicon chips that used a lot less power would make a real difference – again, if chips based on quantum tunneling can take the punishment of rattling around in a military vehicle.
The third trend is at sea, where fully integrated power systems and all-electric ships are becoming popular. Very low-draw electronics options could improve the number of systems operational under emergency power, and also leave more of the ships’ power output available for future items like EMALS electro-magnetic aircraft launch catapults on aircraft carriers, 64 megajoule electro-magnetic rail gun weapons, solid state laser anti-missile turrets, et. al. The chips’ ability to take punishment would be less of a concern in these applications; the naval environment has its own challenges, but naval electronics are contained and insulated.
Above the front lines, we have the realm of space. Extremely low-power transistors would be a huge boon to satellites, and have the potential to dramatically extend a satellite’s potential lifespan. Or allow much smaller power packs, reducing satellite weight, size, and launch costs. Space operations have their own hazards; hardening chips based on quantum tunneling against space radiation, for instance, would present challenges of its own. This field may offer the most visible dollar value for low-power transistors, however, given the cost of building advanced satellites and putting them in orbit.
Behind the front lines, there are data centers. Data centers are beginning to attract attention in both the civilian and military realms, due to their high power costs. Climate control requirements are a significant contributor to those costs, but lower-power silicon chips would influence that, too. Lower power running through the chips means lower heat production as a byproduct, thus reducing both the devices’ power consumption and the power required for climate control.
A $6.4 million contract isn’t very big – but its implications certainly could be.
fn1. The wording of the Jan 18/08 DefenseLINK release was mistaken; it should have read “non-thermionic switching” instead of “on-thermionic.”
Appendix A: STEEP Requirements
The STEEP umbrella program will continue in 3 phases, each having definite and measurable milestones, the most critical of which will be referred to as Go/No-Go (GNG) metrics. Each phase will be capped by a specified device and/or circuit demonstration, which will demonstrate that the goals of the phase have been achieved. Phase 1 asks only for 1-100 working transistors that meet its technical requirements. Phase 2 will refine this design, and move from a transistor to a working circuit with 100 – 10,000 transistors, and power reduction of 100x in off-state and 25x in on-state. Phase 3 will seek to scale the silicon architecture to a high performance 128 kbit SRAM (Standard Random Access Memory) module.
Note that if this research should lead to commercial items of any sort, they will be classified as military equipment under US ITAR arms export regulations (22 CFR, Parts 120-130), with accompanying export, licensing, and personnel requirements. US Export Administration Regulations (15 CFR, Parts 730-799) will also apply. See the FedBizOpps attachment for more specifics.
Appendix B: Additional Readings
- DARPA Broad Agency Announcement (April 3/07) – Steep-subthreshold-slope Transistors for Electronics with Extremely-low Power (STEEP)
- Federal Business Opportunities (BAA07-26) – Steep-subthreshold-slope Transistors for Electronics with Extremely-low Power (STEEP). Includes background attachments.
- 2007 Microsystems Technology Symposium in San Jose, CA – Future of Power Efficient Processing by Dr. Michael Fritze, DARPA MTO [PDF]
- DID (June 25/08) – IBM Working on Wafer-Scale Graphene RF Nanoelectronics. Graphene is one of the non-silicon options for future integrated circuits, using a material with properties similar to carbon nanotubes. In that sense, it can be viewed as one step out beyond STEEP on the technology frontier.